The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Electronic design automation (EDA) tools or applications are generally used by circuit developers to design integrated circuits (ICs). An IC may include many blocks of logic circuitry, registers, memory blocks, input/output (I/O) blocks, etc. These blocks may be configurable to perform different tasks. A generic routing or interconnection structure is typically used to connect the various blocks and circuitries within the IC in different ways. All these configurations are usually done using an EDA tool.
Designing an IC on an EDA tool generally includes, among others, synthesizing and translating the register transfer level (RTL) description of the circuit into a discrete netlist of logic-gate primitives, placing and routing the many components of the synthesized gate-level netlist, and analyzing and simulating the IC design. Routing an FPGA circuit design can be particularly difficult. In digital electronics, the fan-out of a logic gate output is the number of gate inputs connected to a logic gate output. The interconnect circuitry of the FPGA is highly buffered, which leads to a significant number of timing critical, high fan-out nets. Solutions such as register pipelining have been proposed to reduce high fan-out and further increase the performance. During register pipelining, additional registers are inserted between synchronous elements, which lead to an increase in latency at the benefit of increased clock frequencies and throughput. However, performing register pipelining often involves spending significant time and effort because several iterations of locating performance bottlenecks, inserting or removing registers, and compiling the modified integrated circuit design are usually required.